In the field of computer architecture, the concept of a memory hierarchy organized into several levels, based on different speeds and sizes, has grown in popularity. In most cases, each level of a memory hierarchy consists of a smaller, faster (per byte) memory than the level above.
For example, cache memories have proven to be a valuable aid to a computer architecture since the principal of locality holds that programs which reference an item, also tend to reference that same item shortly thereafter. This means that programs tend to favor a portion of their address space. Therefore computer performance can be maximized by tailoring the memory hierarchy in relation to locality and technology.
Recently, random-access memories (RAMs) have been utilized in the memory hierarchy of computer systems as secondary level cache memories. The primary or local cache memory is often integrated onto the same silicon substrate as the microprocessor or the central processing unit of the computer. In these systems, the microprocessor accesses the secondary cache whenever data needed by the program is not found in the local cache memory. Often times, computer systems that employ a secondary cache memory also employ a third level cache memory and/or a main memory such as a hard disk drive data storage unit.
Because the secondary level cache memory frequently resides on a integrated circuit (IC) that is separate from the IC that includes the computer system's microprocessor, there is requirement for separately testing the integrity of the secondary cache memory in various operating modes and test environments. By way of example, the secondary cache memory should first be tested at the die level to ensure proper functionality. This type of testing typically involves running dynamic test patterns at or above the full rated speed of the device. In addition, memory devices must also be tested for functionality as part of normal burn-in reliability verification. In burn-in testing, the device is placed in a high temperature environment for an extended time. During this time the memory army (and much of the associated logic) is toggled to detect defects in the device.
Lastly, power-on self-testing (POST) is utilized to verify to the customer that the cache memory is operational. This test involves a high degree of logic and RAM functionality at close to the full operational speed of the device.
As will be seen the present invention comprises an interface protocol for testing of a cache memory in a computer system. One of the important advantages of the present invention is that it permits a microprocessor to initiate a built-in self-test routine for checking the integrity of the cache memory. The protocol provides status information of the testing procedure back to the microprocessor.